transmitter block diagram

This diagram shows the transmitter section.
It is straight forward. The mixer mixes the signal from the synthesizer with the 10.7 MHz signal from the FM modulator. The result is a 144 MHz signal. This signal is filtered and amplified. I have used several band filters to remove unwanted mix products. Finally the signal is amplified by a power module to 5 Watt. I have cascaded 2 low pass filters to get rid of the harmonics.

Tests with a spectrum analyzer have to be performed to check if the filtering is OK.

block diagram receiver

The receiver design is straightforward. See picture.
Only the squelch circuit is special. The NE604 has a mute input. I made a comparator with discrete components. The comparator checks the level output with the squelch threshold. If the signal is below the threshold the mute is activated.

This receiver had been build a few years ago. It did work but I was not satisfied. It had no squelch, the demodulated signal was weak, it had no preamplifier. The mixer was a BF960. I improved all those issues. Now it works fine.

The preamplifier is a mosfet with a tuned circuit at the gate and one at the drain. It has an issue. When both the input filter as the output filter are peaked at maximum the preamplifier oscillates. So it t needs a small misalignment.
The input is shielded form the output but that does not solve the problem completely.

block diagram PLL

This picture shows the PLL synthesizer. The concept is straight forward.
The VCO signal is mixed with the 132,3 MHz signal from the tripler.
This produces a signal between 1 and 3 MHz. The 4049 programmable divider can handle these frequencies. Phase detection is done by a 4046 phase detector. The reference signal 12.5 KHz comes from a 4060 (f/64) followed by a 74194 divider (f/5).

I have build this synthesizer years ago. The plan was to use it in a transceiver once. So it uses some older ic's. Back then I had some recent experience with these components so used them. If I had to do it again I would use modern components.
I improved several parts of the PLL. For example the step size. It used to be 25 KHz steps.