block diagram PLL

This picture shows the PLL synthesizer. The concept is straight forward.
The VCO signal is mixed with the 132,3 MHz signal from the tripler.
This produces a signal between 1 and 3 MHz. The 4049 programmable divider can handle these frequencies. Phase detection is done by a 4046 phase detector. The reference signal 12.5 KHz comes from a 4060 (f/64) followed by a 74194 divider (f/5).

I have build this synthesizer years ago. The plan was to use it in a transceiver once. So it uses some older ic's. Back then I had some recent experience with these components so used them. If I had to do it again I would use modern components.
I improved several parts of the PLL. For example the step size. It used to be 25 KHz steps.